Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Heretofore, a design instantiated in programmable logic of an FPGA (“FPGA fabric”) was programmed using volatile SRAM cells. It should be appreciated that a relatively complicated circuit instantiated in FPGA fabric may involve programming multiple SRAM cells to store states for programmable logic. On power-off, this information may have been lost unless an FPGA was coupled to an auxiliary power source, such as a battery back-up.
Generally, non-volatile memory products employ flash or electrically erasable programmable read-only memory (“EEPROM”) cells. These cells conventionally involve relatively expensive semiconductor process steps to form their associated double polycrystalline silicon (“poly”) cell structures over an in-process integrated circuit employing Complementary Metal Oxide Semiconductor (“CMOS”) semiconductor logic process.
Accordingly, it would be both desirable and useful to provide a non-volatile SRAM cell for use in an FPGA or other integrated circuit which does not depend on use of EEPROM or flash memory cells.